The present invention relates to a semiconductor integrated circuit device for driving a liquid crystal of a liquid crystal display panel, for a thermal head used for a printer of a facsimile, for driving a step motor of a quartz clock, and for a nonvolatile memory, and to a manufacturing method therefor.
The present invention relates to an electronic circuit using the above semiconductor integrated circuit, and to a manufacturing method therefor.
The present invention relates to an insulating gate field effect type semiconductor integrated circuit having a high withstand voltage construction, more specifically to a driver integrated circuit for driving a liquid crystal, for driving a thermo-sensitive register, and the like.
The present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of driving transistors such as a semiconductor integrated circuit for a thermal head, and having output pads for the driving transistors, respectively.
The present invention relates to a semiconductor circuit device having an external electrically connecting terminal on an electronic circuit.
The present invention relates to a stable operation of a semiconductor integrated circuit device.
The present invention specifically relates to a semiconductor integrated circuit device having bump electrodes on an electronic circuit,
The present invention relates to a semiconductor integrated circuit device having a built-in protecting circuit for protecting internal elements.
The present invention relates to a semiconductor integrated circuit device having bump electrodes.
More specifically, the present invention relates to semiconductor integrated circuit, such as a semiconductor integrated circuit for driving a thermal head, in which the side of a chip is remarkably long as compared with the area of the chip.
The present invention relates to a method of manufacturing a semiconductor integrated circuit, more specifically to a method of manufacturing a semiconductor integrated circuit, such as a semiconductor integrated circuit for driving a thermal head, which is remarkably elongated, and having a long periphery length.
The present invention relates to a semiconductor integrated circuit in which a plurality of transistors are integrated on the same substrate, particularly to a semiconductor integrated circuit in which a pad portion as an external connecting terminal is disposed on a transistor.
The present invention relates to an electronic circuit and a manufacturing method therefor, particularly to an electronic circuit including an integrated circuit which is implemented on a printed circuit board in a face down manner, more specifically to an electronic circuit used for an electronic clock.
The conventional semiconductor device (semiconductor integrated circuit) for a thermal head has a switching function for applying an electric current of about 10 mA through a plurality of resistors of several kxcexa9 arranged in line along a thermal-sensitive paper corresponding to a printing information. The respective thermal-sensitive resistors are electrically connected to an external connecting terminal disposed on a surface of the semiconductor device.
FIG. 2 is a sectional view of an output portion of a general semiconductor device for a thermal head. Thermal-sensitive resistors and semiconductor devices are disposed away from each other in two dimensions on a thermal head substrate. The thermal-sensitive resistors are directly connected to bonded wires 11. The bonded wire 11 is mechanically and electrically connected to a pad region made of an aluminum interconnection by a bonding process. The pad region is comprised of an aluminum film pattern formed, used for connection to the external circuit, by perforating a final passivation film 10 on an aluminum interconnection 9. Below the pad region are disposed an intermediate insulating film 8 and a field insulating film 6 which bear mechanical stress at the bonding process. The aluminum interconnection 9 of the pad region is electrically connected to a drain region of a resistor driving insulating gate field effect transistor arranged in two dimensions through a contact region 12. The drain region, being of a high withstand voltage construction, is comprised of a first drain region 3B comprising a low density impurity region, and a second drain region 3A comprising a high density impurity region. A high voltage of about 30 V is added to the thermal-sensitive resistors in order to apply a large electric current of about 10 mA thereto. Accordingly, when the transistor which functions as a switch is turned off, a high voltage of about 30 V is added to the drain region. A plurality of the transistors for switching the respective thermal-sensitive resistors are arranged along a longitudinal direction of the semiconductor by the number of the resistors in a row as shown in FIG. 3.
An example of the conventional semiconductor device is shown in FIG. 3. FIG. 3 is a plane view of a semiconductor integrated circuit for a thermal head. Output pads O1, O2, . . . , ON and electric source pads P1, P2 and the like are arranged on a periphery of a chip 50. The circuit on which transistors are integrated is arranged away from an external leading electrode in two dimensions. In other words, driving transistors T1, T2, . . . , TN are arranged so as to be electrically connected to the corresponding output pads, and further logic circuits L1, L2, . . . , LN for controlling the respective driving transistors are arranged cycle-periodically along a longitudinal direction of the chip 50. The external leading electrode is comprised of a perforation 92 disposed on the final protecting film and a bump 93 is disposed on the perforation 92. The bump in FIG. 3 may be replaced by a bonding.
FIG. 4 shows a conventional semiconductor integrated circuit device. A plurality of pad electrodes 603 as terminals which are to be connected to the external circuit are disposed on a semiconductor substrate 601. The pad electrodes 603 are connected to an internal electronic circuit 602 through protecting circuits 604, respectively. The protecting circuit 604 aims to discharge an eddy-current in order to prevent the breakdown of the internal electronic circuit 602 due to the eddy-current caused by static electricity and noise inputted to the internal electronic circuit 602 from the external circuit. Basically, one protecting circuit 604 is required for one pad electrode 603. Also, in order to discharge the eddy-current, the protecting circuit 604 is required to be sufficiently away from the internal circuit 602 in such a manner that the discharging electric charge does not reach the internal circuit 602.
However, the conventional semiconductor device for the thermal head has the problems described below. That is, as shown in FIG. 2, the transistors and the bonding pads are required to be disposed away from each other in two dimensions, so that the area of the semiconductor device becomes large, which makes it difficult to lower the manufacturing cost.
Also, the conventional high withstand voltage MOS transistor has a shallow diffusion depth of a low density drain region used for obtaining the high withstand voltage characteristic, which requires the transistor having a large area in order for a large electric current to flow therethrough against the increase of the resistance thereat. Further, when raising the density of the low density drain region for obtaining the high withstand voltage characteristic in order to reduce the resistance thereof, the withstand voltage of the drain region is excessively reduced down to not greater than 10 V. Otherwise, when the diffusion depth is made deeper while remaining the low density, the low density drain region for obtaining the high withstand voltage characteristic excessively becomes large in a lateral direction also, which makes the transistor excessively large.
The conventional semiconductor device shown in FIG. 2 has an disadvantage that, since the active element region on which the transistors are arranged and the external leading electrode are located separately on the individual locations, the area of the chip is large, thereby preventing the reduction in the cost of the chip.
The conventional semiconductor device has a problem that, since the external electrically connecting terminal-use metal electrode is formed larger than the size of the opening portion of the passivation film, on the region in which the external electrically connecting terminal-use metal electrode exists cannot be formed thereover the interconnection of the same metal, thereby preventing the reduction in the chip size.
In the technique of directly implementing a semiconductor integrated circuit on a glass substrate such as COG (Chip on Glass), the semiconductor integrated circuit used for a liquid crystal and the like is exposed to the light entering through the glass of the liquid crystal panel, thereby failing to function properly. As a result, the light shielding is required, and therefore the metal interconnections in the integrated circuit are used as the light shielding film. In a case where the metal interconnections are used in the semiconductor integrated circuit used for the liquid crystal panel, there are caused gaps between the interconnections and the light shielding film region, which makes it impossible to shield the light effectively, since the interconnections are essentially used for the connection between the elements. Also, there are easily caused a case that the voltage of the light shielding film cannot be stabilized, since the light is shielded at a location between the interconnections. In this case, there is unexpectedly caused a floating state, which is not preferable in view of the stable operation.
In the conventional semiconductor device, a pressure is applied to a portion between the external circuit and the semiconductor substrate in order to connect the bump electrode with the external circuit. On this occasion, if the passivation film and the polysilicon resistor are formed below the bump electrode, the passivation film and the polysilicon resistor also are applied with a force, thereby causing cracks on the passivation film to lower the reliability of the semiconductor integrated circuit, and deforming the polysilicon resistor to change the resistance value and therefore lowering the characteristic of the semiconductor integrated circuit.
In the conventional semiconductor device, a pressure is applied to a portion between the bonded wire and the semiconductor substrate in order to connect the external electrically connecting terminal-use aluminum electrode with the bonded wire. On this occasion, if the passivation film and the polysilicon resistor are formed below the bump electrode, the passivation film and the polysilicon resistor also are applied with a force, thereby causing cracks on the passivation film to lower the reliability of the semiconductor integrated circuit, and deforming the polysilicon resistor to change the resistance value and therefore lowering the characteristic of the semiconductor integrated circuit.
The conventional semiconductor device requires the protecting circuits 604 which is identical in number with the pad electrodes 603 as shown in FIG. 4. Then, the protecting circuits 604 are required to be located away from the internal electronic circuits 602, thereby enlarging the area of the protecting circuits 604 which occupy the semiconductor substrate 601 to increase the size of the chip of the semiconductor integrated circuit device, which excessively increases of the cost of the semiconductor integrated circuit device.
The conventional semiconductor integrated circuit, having a dummy bump region, therefore has an drawback to increase the chip size and then increases the cost of the chip.
In the corner portion of the conventional semiconductor integrated circuit device, the silicone substrate on the chip is, before implementation, cut to be shaped like a rectangular. The diffusion region constituting the semiconductor integrated circuit is disposed inside the chip about 40 xcexcm away from the scribed surface.
However, the conventional semiconductor integrated circuit device has a drawback that, since the diffusion region is designed/manufactured to be located not less than 40 xcexcm away from the scribed surface, the chip size is large and therefore the cost of the chip cannot be reduced.
It is found out that the conventional semiconductor integrated circuit device has a drawback to excessively change the characteristic of the integrated circuit due to the static electricity when the pad portion is disposed on the separation region. In other words, when a high voltage is applied to the pad portion as the external connecting terminal, a small amount of electric current unexpectedly flows between electrically separated different N+impurity regions formed in a construction of sandwiching the separation region therebetween, although the detail mechanism is still unclear.
It is known from our experiments that the small amount of electric current is recovered by applying ultraviolet irradiation and high temperature to the semiconductor device. However, there is a problem that it is practically impossible to execute the ultraviolet irradiation on all such occasions.
The conventional integrated circuit using the wire bonding has a problem that the chip size cannot be reduced since the active element region and the pad portion are located on separate regions. Further, there is a problem that, since the pad and the printed circuit board are electrically connected through the bonded wire and the lead, the printed circuit board on which the chips are implemented cannot be sized down. Besides, there are problems that the pad and the printed circuit board are connected by a connection method including three-times connection manner, which cannot be carried out simultaneously, thereby be capable of reducing the manufacturing time. Accordingly, as apparent from the above, the chip and the implemented device cannot be sized down and further the manufacturing processes are long and complicated, whereby the implemented electronic circuit cannot be manufactured at a low cost.
It is, therefore, an object of the present invention to reduce the area of the transistor and the pad and therefore to reduce the manufacturing cost of the device, in order to solve the above-mentioned conventional problems.
Further, it is an object of the present invention to obtain a semiconductor device which is capable of applying a large electric current even with the small area in a high withstand voltage MOS transistor in which a high voltage of not less than 10 V is applied to a drain region.
Still further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor device which is capable of reducing the cost of the device due to the reduction of the chip size.
Also, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which is capable of reducing the size of the chip, on which an external electrically connecting terminal-use metal electrode is formed on an electronic circuit even with the small area without changing the characteristic of the circuit.
Further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor device which, being superior in reliability, has a bump electrode at an electronic circuit without changing the characteristic of the circuit.
Still further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which, being superior in reliability, has an external electrically connecting terminal-use aluminum electrode at an electronic circuit without changing the characteristic of the circuit.
Moreover, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which, being superior in reliability, has an external electrically connecting terminal-use metal electrode at an electronic circuit without changing the characteristic of the circuit.
Further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit which prevents the enlargement of the area of the protecting circuit.
Still further, it is an object of the present invention to solve the above drawbacks then providing a semiconductor integrated circuit device which is capable of reducing the cost of the device due to the reduction of the chip size.
Moreover, it is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device which is capable of reducing the cost of the device due to the reduction of the chip size, more specifically to provide a method of manufacturing a semiconductor integrated circuit device which is capable of reducing the area of the chip of an integrated circuit for a thermal head, or a minute integrated circuit such as a closely contact type line sensor integrated circuit.
Besides, it is an object of the present invention to provide a semiconductor device which prevents the increase of the leak electric current even if the static electricity, which is optionally applied to the pad electrode at the time of the implementation, is applied, in the semiconductor device in which the pad portion is laminated on the transistors in order to reduce the area of the semiconductor integrated circuit.
In is an object of the present invention to solve the above problems then reducing the chip size, sizing down the implemented electronic circuit, improving the manufacturing efficiency of the electronic circuit, and reducing the cost of the device.
The present innovation uses the following means in order to solve the above-mentioned problems.
That is, in a semiconductor integrated circuit comprising a first conductive type semiconductor substrate region disposed on a surface of a support substrate, and a second conductive type insulating gate field effect transistor disposed on a surface of the semiconductor substrate region, and an external electrically connecting terminal disposed so as to be electrically connected to a drain region of the insulating gate field effect transistor through a metal film; the drain region is of a high withstand voltage construction, comprising a first drain region of a second conductive type deep impurity region of low density, and a second drain region of a second conductive type shallow impurity of high density disposed on an inside surface of the first drain region, and the external electrically connecting terminal is partially superposed on the drain region. Also, the external electrically connecting terminal comprises a bump electrode of not less than 10 xcexcm in height, then a gate insulating film of the insulating gate field effect transistor has a film thickness of 100 to 250 xc3x85.
In a semiconductor integrated circuit comprising high withstand insulating gate field effect transistors electrically connected between a plurality of output pads and an earth electrode in open drain construction manner, respectively, a plurality of preamplifier circuits for controlling voltages of gate electrodes of the high withstand voltage insulating gate field effect transistors, and a plurality of latch circuits for supplying signals to a plurality of the preamplifiers, and flip-flip circuits for supplying in order signals to a plurality of the latch circuits; the output pads, the high withstand insulating gate field effect transistors, the preamplifier circuits, the latch circuits, and the flip-flop circuits are arranged in two dimensions cycle-periodically along a longitudinal direction of the semiconductor integrated circuit, and the high withstand voltage insulating gate field effect transistors each is arranged between the output pads.
In a semiconductor integrated circuit comprising a plurality of output pads to which a voltage greater than an electric source voltage, and high withstand voltage driving insulating gate field effect transistors directly electrically connected to drain regions through an extended conductive film of the output pad, respectively; the high withstand voltage driving insulating gate field effect transistors, each having a gate insulating film thickness of 100 to 250 xc3x85 in film thickness, are arranged around the output pad. Also, the high withstand voltage driving insulating gate field effect transistors are arranged line-symmetrically on both sides of the output pads, then the high withstand voltage driving insulating gate field effect transistors are arranged on four sides around the output pad. There is a case that the output pad has a bump. The output pads are arranged in series or in a staggered form along a longitudinal direction of the semiconductor integrated circuit.
In a semiconductor integrated circuit comprising driving insulating gate field effect transistors electrically connected between a plurality of output pads and an earth electrode in open drain construction form, and a plurality of logic circuit cells for controlling voltages of gate electrodes of the driving insulating gate field effect transistors; the output pads, the driving insulating gate field effect transistors and the logic circuit cells are arranged cycle-periodically along a longitudinal direction of the semiconductor device, and the output pads are superposed on the driving insulating gate field effect transistors and the logic circuit cells. Also, there is a case that the output pad comprises a bump electrode disposed on a drain electrode of the driving insulating gate field effect transistor through a barrier metal. There is a case that source electrodes of the driving insulating gate field effect transistors are electrically connected to the barrier metal, respectively. The barrier metal is used as portions of interconnections of the logic circuit cells.
In a semiconductor integrated circuit comprising a semiconductor electronic circuit having insulating gate field effect transistors, an interconnection region and a separation region disposed in the vicinity of a surface of a semiconductor substrate, and an external electrically connecting terminal-use electrode superposed on the semiconductor electronic circuit; a protecting film opening portion for electrically connecting a metal interconnecting layer constituting the electronic circuit and the external electrically connecting terminal-use electrode has a size of not greater than 900 xcfx80xcexcm2 in area. Also, the external electrically connecting terminal-use electrode comprises a bump electrode of not less than 10 xcexcm in height. The protecting film opening portion for electrically connecting the metal interconnecting layer constituting the electronic circuit and the external electrically connecting terminal-use electrode is disposed outside on a location except a center portion of the external electrically connecting terminal-use electrode. The protecting film opening portion for electrically connecting the metal interconnecting layer constituting the electronic circuit and the external electrically connecting terminal-use electrode is superposed on an inside surface of the external electrically connecting terminal-use electrode at one or more locations. The external electrically connecting terminal-use electrode is disposed on the metal interconnecting layer through a barrier metal.
In other words, the area of the external electrically connecting terminal-use metal electrode is made not greater than 400xcfx80 xcexcm2, which realizing the semiconductor integrated circuit device in which the occupied area of the external electrically connecting terminal-use metal electrode is reduced.
On this occasion, the semiconductor electronic circuit comprises an integrated circuit for driving an exothermic body of a thermal printing head. Further, the semiconductor electronic circuit comprises an integrated circuit for driving a liquid crystal of a liquid crystal display panel. The semiconductor electronic circuit comprises an integrated circuit for driving a step motor of a quartz clock. The semiconductor electronic circuit comprises a nonvolatile memory integrated circuit.
When the external electrically connecting terminal-use metal electrode is constructed as described above, the metal interconnecting layer can be superposed on a lower surface of the solder bump external electrically connecting terminal-use electrode or gold bump electrode, which realizing the semiconductor integrated circuit device having a small chip size.
A semiconductor integrated circuit comprises first and second metal electrodes disposed away from each other on a substrate, a metal interconnection made of the same metal as the first and second metal electrodes, a final protecting film disposed on a surface of the substrate including the metal interconnection, a perforation region of the final protecting film disposed on the first and second electrodes, and a barrier metal film interconnected on the perforation region of the final protecting film and the final protecting film between the first and second metal electrodes so as to electrically connect the first and second metal electrodes. Also, a metal of a bump construction is disposed on the barrier metal film. The barrier metal film has a plane pattern in which a plurality of circle patterns are connected in series.
In a semiconductor integrated circuit having a bump and a barrier metal film below the bump; the barrier metal film is disposed also on a semiconductor element. In other words, the bump, and the barrier metal used for preventing the counter diffusion with the pad are arranged not only below but also on the semiconductor element, thereby enabling the light shielding.
A bump electrode arranged on an electronic circuit comprises a plurality of matrix-like bump electrodes for a single electric electrode, then a bump electrode arranged on an electronic circuit comprises a plurality of line-like bump electrodes for a single electric electrode. Also, a bump electrode arranged on an electronic circuit has a gap therein. A bump electrode arranged on an electronic circuit is shaped like a comb.
In other words, (1) the bump electrode is divided into a plurality of pieces, which provides the semiconductor integrated circuit device having the bump electrodes in which the stress applied to the integrated circuit can be distributed;
(2) two dimensional gaps are formed in the bump electrode, which provides the semiconductor integrated circuit device having the bump electrode in which the stress applied to the integrated circuit can be distributed; and
(3) gaps are formed on the periphery portion of the bump electrode, which provides the semiconductor integrated circuit device having the bump electrode in which the stress applied to the integrated circuit can be distributed.
In an external electrically connecting terminal-use electrode disposed on an electronic circuit element, the external electrically connecting terminal-use electrode has a gap, or is shaped like a lattice, a continuous rectangle, or a curve.
In other words, (4) gaps are formed in the external electrically connecting terminal-use aluminum electrode, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit can be distributed;
(5) the external electrically connecting terminal-use aluminum electrode is shaped like a plurality of continuously rectangle, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit can be distributed; and
(6) the external electrically connecting terminal-use aluminum electrode is shaped like a plurality of protrusions, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit can be distributed.
In a semiconductor integrated circuit having an external electrically connecting terminal-use electrode disposed on an electronic circuit element, the external electrically connecting terminal-use electrode has a convexoconcave portion at a surface thereof, a convexoconcave portion on a surface of the external electrically connecting terminal-use electrode is formed by a construction film just below the external electrically connecting terminal, is formed by a separation insulating film just below the external electrically connecting terminal-use electrode, or is formed by another interconnecting material just below the external electrically connecting terminal-use electrode, or a convexoconcave portion on a surface of the external electrically connecting terminal-use electrode is shaped like one or more polygons, or like concentric circles or spiral.
In other words, (7) a plurality of protrusions are disposed in the external electrically connecting terminal-use aluminum electrode, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit at the time of the implementation of the bonded wire can be distributed. (8) A plurality of protrusions are disposed on a film just below the external electrically connecting terminal-use aluminum electrode, thereby forming a convexoconcave portion on a surface of the external electrically connecting terminal-use aluminum electrode, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit at the time of the implementation of the bonded wire can be distributed. (9) A line-like or curved convexoconcave portion is formed on a surface of the external electrically connecting terminal-use aluminum electrode, which provides the semiconductor integrated circuit device having the external electrically connecting terminal-use aluminum electrode in which the stress applied to the integrated circuit at the time of the implementation of the bonded wire can be distributed.
The external electrically connecting terminal-use aluminum electrode is constructed by one or a combination of the above constructions, thereby distributing the stress on the implementation of the device, which is capable of providing a semiconductor integrated circuit of high reliability, having the external electrically connecting terminal-use aluminum electrode on the elecronic circuit which does not change the characteristic of the circuit.
In a semiconductor integrated circuit having a bump electrode, the bump electrode is disposed on an electronic circuit, the bump electrode has a hollow portion, the hollow portion of the bump electrode is embedded by a material softer than that of the bump electrode. The hollow portion of the bump electrode is embedded by a polyimide resin, or the hollow portion of the bump electrode is embedded by a photoresist.
In other words, (10) a hollow portion is disposed in the bump electrode, which provides the semiconductor integrated circuit device having the bump electrode in which the stress applied to the integrated circuit can be distributed; and (11) a region made of a materiel softer than that of the bum electrode is disposed in the bump electrode, which provides the semiconductor integrated circuit device having the bump electrode in which the stress applied to the integrated circuit can be distributed.
According to the above construction, the stress on the implementation of the device is distributed, which is capable of providing a semiconductor integrated circuit of high reliability, having the bump electrode on the elecronic circuit which does not change the characteristic of the circuit.
A semiconductor integrated circuit having an external electrically connecting terminal-use electrode is disposed on an electronic circuit element, and then an insulating film just below the external electrically connecting terminal-use electrode is made of a polyimide resin.
In other words, a layer of a polyimide resin is disposed between the external electrically connecting terminal-use aluminum electrode and the plasma nitride film for the passivation film.
According to the above construction, the stress at the time of the implementation of the device is absorbed, which is capable of providing a semiconductor integrated circuit of high reliability, having the external electrically connecting terminal-use aluminum electrode on the elecronic circuit which does not change the characteristic of the circuit.
In a semiconductor integrated circuit comprising a semiconductor electronic circuit having insulating gate field effect transistors an interconnection region and a separation region disposed in the vicinity of a surface of a semiconductor substrate, and an external electrically connecting terminal-use electrode superposed on the semiconductor electronic circuit; a metal interconnecting layer constituting the semiconductor electronic circuit has a film thickness of 2 to 4 xcexcm, then a bump electrode of not less than 10 xcexcm in height is disposed on the external electrically connecting terminal-use electrode. The aluminum interconnecting layer serves as the electrode of the external electrically connecting terminal. The semiconductor electronic circuit comprises an integrated circuit for driving an exothermic body of a thermal printing head. The semiconductor electronic circuit comprises an integrated circuit for driving a liquid crystal of a liquid display panel. The semiconductor electronic circuit comprises an integrated circuit for driving a step motor of a quartz clock. The semiconductor electronic circuit comprises a nonvolatile memory integrated circuit.
In other words, the external electrically connecting terminal-use metal electrode is formed so as to have a thick film of not less than 2 xcexcm, which provides a semiconductor integrated circuit having the external electrically connecting terminal-use metal electrode in which the stress applied to the semiconductor integrated circuit at the time of the implementation of the bonded wire can be reduced.
The external electrically connecting terminal-use metal electrode is constructed according to the above-mentioned construction, thereby distributing the stress at the time of the implementation, which is capable of providing a semiconductor integrated circuit of high reliability, having the external electrically connecting terminal-use metal electrode on the elecronic circuit which does not change the characteristic of the circuit.
In a semiconductor integrated circuit comprising a plurality of pad electrodes to which a signal is inputted from an external portion, a plurality of protecting circuits connected to the pad electrodes, respectively, for discharging an eddy-current generating due to the signal inputted from the pad electrode, and an internal circuit for processing the external portion signal from the external portion inputted through a plurality of the pad electrodes and a plurality of the protecting circuits; another circuit element is interposed between at least one out of a plurality of the pad electrodes and the protecting circuit corresponding to the pad electrode. In a semiconductor integrated circuit device comprising a plurality of pad electrodes to which a signal is inputted from an external portion, a plurality of protecting circuits connected to the pad electrodes, respectively, for discharging an eddy-current generating due to the signal inputted from the pad electrode, and an internal circuit for processing the external portion signal inputted from the external portion through a plurality of the pad electrodes and a plurality of the protecting circuits; at least two out of a plurality of the protecting circuits are arranged as one or more blocks. Further, an interconnection connecting the pad electrode and the protecting circuit is arranged on a portion of a surface of the internal circuit through an insulating film.
In other words, the protecting circuit and the pad electrode are separated from each other, thereby laying out the protecting circuit freely, which groups a plurality of the protecting circuits into a block to provide the semiconductor integrated circuit device in which the area of the protecting circuits is small.
In a semiconductor integrated circuit device having bump electrodes and dummy bump electrodes; the dummy bump electrodes are arranged on an electronic circuit, then an area of the dummy bump electrode is greater than that of the bump electrode. An area of the dummy bump electrode is less than that of the bump electrode, and the dummy bump electrodes are arranged in a matrix-like manner. Further, dummy electrode has one or more gaps.
In a semiconductor integrated circuit device having bump electrodes and dummy bump electrodes; the dummy bump electrodes are arranged on an electronic circuit, and the dummy bump electrodes are arranged on a periphery of a semiconductor substrate.
In other words, the dummy bumps are disposed on the semiconductor integrated circuit so as to be, irrespective of whether the diffusion region or the interconnection region, superposed on a part of, or all of it.
(12) In a method of manufacturing a semiconductor integrated circuit comprising the steps of forming a plurality of transistors on a surface of a semiconductor region of a wafer, metal-interconnecting electrodes of the transistors, forming a protecting film on the metal interconnection, and cutting the wafer along a scribe region of the water; the wafer cutting step comprises a first cutting step and a second cutting step, and a cutting speed in the first cutting step is less than that in the cutting step.
(13) There is provided a method of manufacturing a semiconductor integrated circuit described in (12), characterized in that the cutting in the first cutting step is carried out by a chemical means. (13) There is provided a method of manufacturing a semiconductor integrated circuit described in (12), a surface of the semiconductor region is cut more deeply than the transistor at the first cutting process. (14) There is provided a method of manufacturing a semiconductor integrated circuit described in (12), a surface of the semiconductor region is cut in a V-like form at the first cutting process. (15) There is provided a method of manufacturing a semiconductor integrated circuit described in (12), an average width of the semiconductor region cut at the first cutting process is made greater than that of the semiconductor region cut at the second cutting process.
In a semiconductor integrated circuit having an electronic circuit on a surface of a first conductive type semiconductor region of a substrate, the substrate being separated into chips by scribe; a stepped region is disposed on the substrate along a scribed surface on a side surface of the chip. The stepped region is deeper than a second conductive type diffusion region constituting the electronic circuit. Further, an external electrically connecting terminal is disposed on a transistor constituting the electronic circuit.
In a semiconductor integrated circuit having a plurality of field effect transistors disposed on a surface of a substrate so as to separated electrically by a separation region, and an external connecting terminal laminated on a part out of a plurality of the field effect transistors; a shield electrode is disposed on the separation region below the external connecting terminal. Also, the external connecting terminal comprises a bump electrode. Further, in a semiconductor integrated circuit having a plurality of field effect transistors disposed on a surface of a substrate so as to be separated electrically by a separation region, and an external connecting terminal laminated on a part out of a plurality of the field effect transistors; an inversion preventing high density impurity region is disposed at an intermediate location of the separation region below the external connecting terminal. Further, in a semiconductor integrated circuit having a plurality of field effect transistors disposed on a surface of a substrate so as to be separated electrically by a separation region, and an external connecting terminal laminated on a part out of a plurality of the field effect transistors, there is included a separation construction in which the separation region below the external connecting terminal and the separation region below a portion except the external connecting terminal.
In an electronic circuit comprising a printed circuit board in which a metal interconnection is disposed on a surface of an insulating substrate, and a semiconductor integrated circuit in which an external connecting terminal is electrically connected to the metal interconnection on a surface of the printed circuit substrate; the external connecting terminal is disposed on active element region of the semiconductor integrated circuit. The external connecting terminal comprises a bump electrode. In a method of manufacturing a semiconductor integrated circuit, comprising the steps of working an integrated circuit on a surface of a semiconductor wafer, forming a protecting film on a surface of the integrated circuit, perforating a portion of the protecting film to form a pad possession as an external connecting terminal region, forming a solder bump electrode on the pad portion, and scribing the semiconductor electrode to be made into a chip, spaying a resin flux cored solder on a surface of the solder bump electrode located on a surface of the chip, adhering the chip to the printed circuit board to be implemented, in a face down manner at a predetermined location at which the solder bump electrode and a metal interconnection of the printed circuit board are superposed to each other, heating the chip from a rear surface of the chip, and forming a shielding film on a surface of the chip. The chip heating step comprises a step of applying a heated wind to the rear surface of the chip.
As described above, a portion of the transistor and the pad region as the output terminal can be superposed in two dimensions, which has an effect to reduce the area of the chip to reduce the manufacturing cost. Also, the distance between the gate electrode of the transistor and the contact hole of the drain region can be increased, which has an effect to reduce the electrostatic withstand voltage.
Further, even in the metal interconnection comprising one layer, the area of the external electrically connecting terminal-use metal electrode is made small, thereby superposing the metal interconnecting layer on a lower surface of the external electrically connecting terminal-use solder bump electrode or the gold bump electrode, which is capable of providing the semiconductor integrated circuit device in which the chip size is small.
Moreover, the light is shielded by the barrier metal even in the metal interconnection comprising one layer, so that the semiconductor never fail to function properly.
The bump electrode is constructed by one or a combination of the above constructions, thereby distributing the stress at the time of the implementation of the device, which is capable of providing a semiconductor integrated circuit of high reliability, having the bump electrode on the elecronic circuit which does not change the characteristic of the circuit.
Besides, in the semiconductor integrated circuit device constructed as above, the dummy bumps are arranged freely, thereby reducing the size of the semiconductor integrated circuit device.
In the semiconductor integrated circuit constructed as above, the crystal defect in the vicinity of the scribed surface induced by scribing is hard to be caused up to the diffusion region. Accordingly, the distance between the scribed surface and the diffusion region in two dimensions can be reduced.